The down converters in wireless communication systems perform a transformation of a radio frequency (RF) signal into a baseband signal centered at zero frequency. In high performance equipment, digital down converters are used where an analog RF signal is converted into a digital signal followed by processing in digital form. Typically, a high speed ADC is used because of the high frequency RF signals.
High speed analog to digital converters are typically built as composite ADCs that consist of a number of time interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude and phase/frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions (“Type 1 distortions”), for example, in the form of spurious frequency components. In the prior art, in order to prevent these distortions, equalization of the responses of the sub-ADCs is used (see, for example, U.S. Pat. No. 7,408,495).
Additional signal distortions (“Type 2 distortions”) are due to deviations of the amplitude and phase/frequency responses of the respective ADCs, averaged over the set of the sub-ADCs, from ideal responses. In general, an equalizer for correcting for such distortions, is required to perform two functions: (i) compensate for mismatches of the frequency responses of the sub-ADC's, and (ii) line up the averaged frequency responses of the ADC.
A block diagram of a conventional digital down converter 8, with an equalizer 12, is shown in FIG. 1. In down converter 8, an input RF signal is applied to the input of a composite ADC 10 (including interleaved sub-ADCs, not shown). ADC 10 transforms the input RF signal into a digital signal, which is applied at an input of equalizer 12. It is important to note that the equalizer 12 is positioned upstream with respect to any signal down conversion, and thus must operate at high frequency, particularly for RF input signals.
Mismatches of the frequency responses of the interleaved sub-ADCs of the composite ADC 10, and deviations from the average frequency responses of the ADC 10 are corrected by equalizer 12. The output of equalizer 12 is applied to in-phase input 16A and quadrature input 16B of an I/Q demodulator 16. I/Q demodulator 16 includes two mixers 20A and 20B which mix the signals at inputs 16A and 16B with an output of a local oscillator 24, operating at a local oscillator frequency FLO with two sinusoidal outputs having a phase difference of 90°. Outputs of mixers 20A and 20B are applied to a respective ones of low pass filter I 28A and low pass filter Q 28B, and then to a respective one of decimator I 30A and decimator Q 30B, to produce respective baseband outputs labeled as In-Phase Output I and Quadrature Output Q in FIG. 1.
Most down converter applications (such as wireless terminals of different communication systems, radar systems and the like) require real time processing of a received input signal. The necessity to operate in a real time mode imposes restrictions on the bulk of computing resources implemented in the hardware. Equalizer 12, in the down converter of the type illustrated by the block diagram of FIG. 1, is usually built as a conventional FIR filter. The most resources-consuming components of the FIR filter are multipliers. Because of the difference between the RF signal frequency (usually several GHz) and the frequency of operation of present-day FPGAs (up to 200-250 MHz), each multiplication in the FIR is carried out by a group of multipliers connected in parallel. The required number of multipliers becomes a main reason that makes it impossible to build an equalizer that operates in a real time mode.
In US Patent Application Publication US2015/0200679 A1, an improved equalizer structure is proposed, where the calculations are transferred from a high frequency region at an ADC output to low frequency down converted signals I/Q. In that way, a reduction of required computation resources is achieved. However, equalization of ADC responses as there-described, is performed in the entire frequency range of the ADC output, even though the down converter uses only frequencies located in the frequency band of the received input signal. As a consequence, a considerable portion of the performed calculations turn out to be redundant, and it remains difficult to build a down converter with an equalizer operating in a real time mode.
A structure of a down converter that is different from that of the block diagram of FIG. 1, was suggested in European Patent Application EP 2 773 045 A1. In that application, an adaptive algorithm is used that comprises a tracing mechanism for detection of statistical parameters of a processing signal. The found statistical parameters are employed to perform signal correction that extinguishes the spurious components. Since all operations in the corresponding device are done at the ADC sampling frequency, the required resources are the same as in the block diagram of FIG. 1 (or even more because of additional units of the tracing mechanism).
Overall, the prior art does not provide methods for ADC digital equalization in frequency down converters which enables high speed, real time operation.